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nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram 1 rev 1.1 consumer oct 2010 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. features ? high performance: ? single pulsed ras interface ? fully synchronous to positive clock edge ? four banks controlled by ba0/ba1 (bank select) ? programmable cas latency: 2, 3 ? programmable burst length: 1, 2, 4, 8 or full page ? programmable wrap: sequential or interleave ? multiple burst read with single write option ? automatic and controlled precharge command ? data mask for read/write control (x4, x8) ? dual data mask for byte control (x16) ? auto refresh (cbr) and self refresh ? suspend mode and power down mode ? standard power operation ? 8192 refresh cycles/64ms ? random column address every ck (1-n rule) ? single 3.3v 0.3v power supply ?lvttl compatible ? package: 54-pin 400 mil tsop-type ii ? lead-free & halogen-free product available description the nt5sv32m8cs and nt5sv16m16cs are four-bank synchronous drams organized as 16mbit x 4 i/o x 4 bank, 8mbit x 8 i/o x 4 bank, and 4mbit x 16 i/o x 4 bank, respec- tively. these synchronous devices achieve high-speed data transfer rates of up to 166mhz by employing a pipeline chip architecture that synchronizes the output data to a system clock. the device is designed to comp ly with all jedec standards set for synchronous dram products, both electrically and mechanically. all of the control, address, and data input/out- put (i/o or dq) circuits ar e synchronized with the positive edge of an externally supplied clock. ras , cas , we , and cs are pulsed signals which are exam- ined at the positive edge of each externally applied clock (ck). internal chip operating modes are defined by combina- tions of these signals and a command decoder initiates the necessary timings for each operation. a fifteen bit address bus accepts address data in the conventional ras /cas mul- tiplexing style. thirteen row addresses (a0-a12) and two bank select addresses (ba0, ba1) are strobed with ras . eleven column addresses (a0-a9, a11) plus bank select addresses and a10 are strobed with cas . column address a11 is dropped on the x8 device, and column addresses a11 and a9 are dropped on the x16 device. prior to any access operation, the cas latency, burst length, and burst sequence must be programmed into the device by address inputs a0-a12, ba0, ba1 during a mode register set cycle. in addition, it is possib le to program a multiple burst sequence with single write cycl e for write through cache operation. operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard drams. a sequential and gap- less data rate of up to 166mhz is possible depending on burst length, cas latency, and speed grade of the device. auto refresh (cbr) and self refresh operation are sup- ported. 6k/6ki cl=3 75b/75bi cl=3 units f ck clock frequency 166 133 mhz t ck clock cycle 6 7.5 ns t ac clock access time 1 ??ns t ac clock access time 2 55.4ns 1. terminated load. see ac characteristics on page 37 2. unterminated load. see ac characteristics on page 37 3. t rp = t rcd = 2 cks
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 2 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. nanya technology corporation hwa ya technology park 669 fu hsing 3rd rd., kueishan, taoyuan, 333, taiwan, r.o.c. tel: +886-3-328-1688 please visit our home page for more information: www.nanya.com ordering information organization part number speed grade package power clock frequency cl - t rcd - t rp note 32m x 8 nt5sv32m8cs-6k 166mhz-3-3-3 pc166 400mil 54-pin tsop ii 3.3v 16m x 16 nt5sv16m16cs-6k 32m x 8 nt5sv32m8cs-75b 133mhz-3-3-3 pc133 16m x 16 nt5sv16m16cs-75b 32m x 8 nt5sv32m8cs-6ki 166mhz-3-3-3 pc166 16m x 16 NT5SV16M16CS-6KI 32m x 8 nt5sv32m8cs-75bi 133mhz-3-3-3 pc133 16m x 16 nt5sv16m16cs-75bi cl = cas latency
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 3 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c pin assignments for planar components (top view) 54-pin plastic tsop(ii) 400 mil 8mbit x 8 i/o x 4 bank 1 2 3 4 5 6 9 10 11 12 13 14 7 8 15 16 17 18 19 20 21 22 54 53 52 51 50 49 46 45 44 43 42 41 48 47 40 39 38 37 36 35 34 33 v dd dq0 v ddq nc dq1 v ssq v ddq nc dq3 v ssq nc v dd nc dq2 nc we cas ras cs ba0 ba1 v ss dq7 v ssq nc dq6 v ddq v ssq nc dq4 v ddq nc v ss nc dq5 nc dqm ck cke a12 a11 a9 23 24 25 32 31 30 a10/ap a0 a1 a2 a8 a7 a6 a5 26 27 29 28 a3 v dd a4 v ss v dd dq0 v ddq dq1 dq2 v ssq v ddq dq5 dq6 v ssq dq7 v dd dq3 dq4 ldqm we cas ras cs ba0 ba1 a10/ap a0 a1 a2 a3 v dd v ss dq15 v ssq dq14 dq13 v ddq v ssq dq10 dq9 v ddq dq8 v ss dq12 dq11 nc udqm ck cke a12 a11 a9 a8 a7 a6 a5 a4 v ss 4mbit x 16 i/o x 4 bank
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 4 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. pin description ck clock input dq0-dq15 data input/output cke (cke0, cke1) clock enable dqm, ldqm, udqm data mask cs chip select v dd power (+3.3v) ras row address strobe v ss ground cas column address strobe v ddq power for dqs (+3.3v) we write enable v ssq ground for dqs ba1, ba0 bank select nc no connection a0 - a12 address inputs ? ? input/output functional description symbol type polarity function ck input positive edge the system clock input. all of the sdram input s are sampled on the rising edge of the clock. cke, cke0, cke1 input active high activates the ck signal when high and deactivates the ck signal when low. by deactivating the clock, cke low initiates the power down mode, suspend mode, or the self refresh mode. cs input active low cs enables the command decoder when low and disabl es the command decoder when high. when the command decoder is disabled, new commands ar e ignored but previous operations continue. ras , cas , we input active low when sampled at the positive rising edge of the clock, cas , ras , and we define the operation to be executed by the sdram. ba1, ba0 input ? selects which bank is to be active. a0 - a12 input ? during a bank activate command cycle, a0-a12 defines the row address (ra0-ra12) when sam- pled at the rising clock edge. during a read or write command cycle, a0-a9 and a11 defines the column address (ca0-ca9, ca11), when sampled at the rising cl ock edge. assume the x4 organization. a10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. if a10 is high, auto-precharge is selected and ba0, ba1 defines the bank to be precharged. if a10 is low, autoprecharge is disabled. during a precharge command cycle, a10 is used in conjunction with ba0, ba1 to control which bank(s) to precharge. if a10 is high, all banks will be prec harged regardless of the state of bs. if a10 is low, then ba0 and ba1 are used to define which bank to precharge. dq0 - dq15 input- output ? data input/output pins operate in the same manner as on conventional drams. dqm ldqm udqm input active high the data input/output mask places the dq buffers in a high impedance state when sampled high. in x16 products, the ldqm and udqm control the lowe r and upper byte i/o buffe rs, respectively. in read mode, dqm has a latency of tw o clock cycles and controls the output buffers like an output enable. dqm low turns the output buffers on and dq m high turns them off. in write mode, dqm has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if dqm is high. v dd , v ss supply ? power and ground for the input buffers and the core logic. v ddq v ssq supply ? isolated power supply and ground for the output buffers to provide im proved noise immunity.
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 5 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c block diagram dq 0 dq x data input/output buffers cke buffer ck buffer k e ck cs ras cas dqm we command decoder mode register counter column address counter refresh a1 a2 a3 a4 a5 a6 a7 a10 a8 a9 a0 a11 sense amplifiers memory bank 1 cell array row decoder address buffers (15) column decoder sense amplifiers memory bank 3 cell array row decoder column decoder sense amplifiers memory bank 0 cell array row decoder column decoder sense amplifiers memory bank 2 cell array row decoder column decoder data control circuitry ba0 ba1 control signal generator cell array, per bank, for 8mb x 8 dq: 8192 row x 1024 col x 8 dq (dq0-dq7) . cell array, per bank, for 4mb x 16 dq: 8192 row x 512 col x 16 dq (dq0-dq15). a12
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 6 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. power on and initialization the default power on state of the mode register is supplie r specific and may be undefined. the following power on and initializ a- tion sequence guarantees the device is prec onditioned to each users specific needs. like a conventional dram, the synchronous dram must be powered up and initialized in a predefined manner. during power on, all v dd and v ddq pins must be built up simultaneous ly to the specified voltage when the input signals are held in the ?nop? state. the power on voltage must not exceed v dd +0.3v on any of the input pins or v dd supplies. the ck signal must be started at the same time. after power on, an initial pause of 200 s is required followed by a precharge of all banks using the precharge command. to prevent data contention on t he dq bus during power on, it is required that the dqm and cke pins be held high during the initial pause period. once all banks have been prec harged, the mode register set co mmand must be issued to ini- tialize the mode register. a minimum of tw o auto refresh cycles (cbr) are also required. these may be done before or after programming the mode register. failure to follow these steps may lead to unp redictable start-up modes. programming the mode register for application flexibility, cas latency, burst length, burst sequence, and operati on type are user defined variables and must be programmed into the sdram mode register with a single mode re gister set command. any cont ent of the mode register can be altered by re-executing the mode register set command. if the user chooses to modify only a subset of the mode register variables, all four variables must be redefined when the mode register set command is issued. after initial power up, the mode register set command must be i ssued before read or write cycl es may begin. all banks must be in a precharged state and cke must be high at least one cycl e before the mode register se t command can be issued. the mode register set command is activated by the low signals of ras , cas , cs , and we at the positive edge of the clock. the address input data during this cycle defines the parameters to be set as shown in the mode register operation table. a new command may be issued following the mode register set command once a delay equal to t rsc has elapsed. cas latency the cas latency is a parameter that is used to define the delay from when a read command is registered on a rising clock edge to when the data from that read command becomes available at the outputs. the cas latency is expressed in terms of clock cycles and can have a value of 2 or 3 cycles. the value of the cas latency is determined by the speed grade of the device and the clock frequency that is used in the application. a table showing the relationship between the cas latency, speed grade, and clock frequency appears in the electrical characteri stics section of this docum ent. once the appropriate cas latency has been selected it must be progra mmed into the mode register after power up, for an explanation of this procedure see programming the mode regist er in the previous section.
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 7 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c mode register operation (a ddress input for mode set) a11 a3 a4 a2 a1 a0 a10a9a8a7a6a5 address bt burst length cas latency mode cas latency m6 m5 m4 latency 0 0 0 reserved 0 0 1 reserved 010 2 011 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved burst length m2 m1 m0 length sequential interleave 000 1 1 001 2 2 010 4 4 011 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved burst type m3 type 0 sequential 1 interleave operation mode m14 m13 m12 m11 m10 m9 m8 m7 mode 00000000 normal 00000100 multiple burst with single write operation mode ba0 ba1 bus (ax) register(mx) a12
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 8 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. burst mode operation burst mode operation is used to provide a c onstant flow of data to memory location s (write cycle), or from memory locations (read cycle). there are three parameters that define how the burst mode will operate. these parameters include burst sequence, burst length, and operation mode. the burst sequence and burst length are programm able, and are determined by address bits a0 - a3 during the mode register set command. oper ation mode is also programmable and is set by address bits a7 - a12, ba0, and ba1. the burst type is used to define the order in which the burst data will be delivered or stored to the sdram. two types of burst sequences are supported, sequential a nd interleaved. see the table below. the burst length controls the nu mber of bits that will be output after a read comm and, or the number of bits to be input after a write command. the burst length can be progra mmed to have values of 1, 2, 4, 8 (a ctual page length is dependent on organi- zation: x4, x8, or x16). burst operation mode can be normal operation or multiple burst wi th single write operation. no rmal operation implies that the device will perform burst operations on both read and writ e cycles until the desir ed burst length is sati sfied. multiple burst with single write operation was added to support write through cache oper ation. here, the programmed bur st length only applies to read cycles. all write cycles are single writ e operations when this mode is selected. note: page length is a function of i/o organization and column addressing. x8 organization (ca0-ca9); page length = 1024 bits x16 organization (ca0-ca8); page length = 512 bits burst length and sequence burst length starting address (a2 a1 a0) sequential a ddressing (decimal) interl eave addressing (decimal) 2 x x 0 0, 1 0, 1 x x 1 1, 0 1, 0 4 x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 x 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 256 (full page) n cn, cn+1,cn+2... not supported
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 9 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c bank activate command in relation to the operation of a fast page mode dram, the bank activate command correlates to a falling ras signal. the bank activate command is issued by holding cas and we high with cs and ras low at the rising edge of the clock. the bank select address ba0 - ba1 is used to select the desired bank. the row ad dress a0 - a12 is used to determine which row to activate in the selected bank. the bank activate command must be applied before any read or write operation can be exec uted. the delay from when the bank activate command is applied to when the first read or write operation can begin must meet or exceed the ras to cas delay time (t rcd ). once a bank has been activated it must be precha rged before another bank activate command can be applied to the same bank. the minimum time interval between successive bank activate commands to the same bank is deter- mined by the ras cycle ti me of the device (t rc ). the minimum time inte rval between interleaved bank activate commands (bank a to bank b and vice versa) is the bank to bank delay time (t rrd ). the maximum time that each bank can be held active is specified as t ras(max) . bank select the bank select inputs, ba0 and ba1, determine the bank to be used during a bank activate, pr echarge, read, or write oper- ation. bank activate command cycle bank selection bits ba0 ba1 bank 0 0 bank 0 1 0 bank 1 0 1 bank 2 1 1 bank 3 address ck t0 t2 t1 t3 tn tn+1 tn+2 tn+3 command nop nop nop nop bank a row addr. bank a activate write a with auto bank a col. addr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bank b activate bank a row addr. bank a activate ras -cas delay ( t rcd ) : ?h? or ?l? ras cycle time ( t rc ) precharge ras - ras delay time ( t rrd ) bank b row addr. (cas latency = 3, t rcd = 3)
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 10 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. read and write access modes after a bank has been activated, a read or write cycl e can be executed. this is accomplished by setting ras high and cas low at the clock?s rising edge after the necessary ras to cas delay (t rcd ). we must also be defined at this time to determine whether the access cycle is a read operation (we high), or a write operation (we low). the address inputs determine the start- ing column address. the sdram provides a wide variety of fast access modes. a single read or write command will initiate a serial read or write operation on successive clock cycles up to 13 3 mhz for pc133 or upto 1 66mhz for pc166 devices. the number of serial data bits for each access is equal to the burst length , which is programmed in to the mode register. similar to page mode of co nventional drams, a read or writ e cycle can not begin until the sens e amplifiers latch the selected row address information. the refresh period (t ref ) is what limits the number of random column accesses to an activated bank. a new burst access can be done even before the previous burst ends. the ability to interrupt a burst operation at every clock cycle is supported; this is referred to as the 1-n rule. when the previous burst is interrupt ed by another read or write com- mand, the remaining addresses are overridden by the new address. precharging an active bank after each read or write operation is not necessary providing the same row is to be accessed again. to perform a read or write cycle to a different row within an acti vated bank, the bank must be precharged and a new bank acti- vate command must be issued. when more than one bank is activa ted, interleaved (ping pong) bank read or write operations are possible. by using the programmed burst length and alte rnating the access and precharge operations between multiple banks, fast and seamless data access operation among many diffe rent pages can be realized. when multiple banks are acti- vated, column to column interleave operation can be done bet ween different pages. finally, read or write commands can be issued to the same bank or between active banks on every clock cycle.
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 11 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c burst read command the burst read command is initiated by having cs and cas low while holding ras and we high at the rising edge of the clock. the address inputs determine the starting co lumn address for the burst, the mode regi ster sets the type of burst (sequential or interleave) and the burst length (1, 2, 4, 8). the delay from t he start of the command to when the data from the first cell app ears on the outputs is equal to the value of the cas latency that is set in the mode register. read interrupted by a read a burst read may be interrupted before completion of the burst by another read command, with t he only restriction being that the interval that separates the commands must be at least one clock cycle. when the previous burst is interrupted, the remain- ing addresses are overridden by the new address with the full burst length. the data from the first read command continues to appear on the outputs until the cas latency from the interrupting read command is satisfied, at this point the data from the interrupting read command appears. burst read operation read interrupted by a read command read a nop nop nop nop nop nop nop dout a 0 cas latency = 2 t ck3 , dqs cas latency = 3 dout a 1 dout a 2 dout a 3 nop ck t0 t2 t1 t3 t4 t5 t6 t7 t8 t ck2 , dqs dout a 0 dout a 1 dout a 2 dout a 3 (burst length = 4, cas latency = 2, 3) command read a read b nop nop nop nop nop nop t ck2 , dqs cas latency = 2 t ck3 , dqs cas latency = 3 nop ck t0 t2 t1 t3 t4 t5 t6 t7 t8 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 (burst length = 4, cas latency = 2, 3)
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 12 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. read interrupted by a write to interrupt a burst read with a write command, dqm may be neede d to place the dqs (output dr ivers) in a high impedance state to avoid data cont ention on the dq bus. if a read co mmand will issue data on the firs t or second clo cks cycles of the write operation, dqm is needed to insure the dqs are tri-stated . after that point the write command will have control of the dq bus. minimum read to write interval command nop nop read a write a nop nop nop dqm din a 0 din a 1 din a 2 din a 3 : ?h? or ?l? din a 0 din a 1 din a 2 din a 3 t ck2 , dqs cas latency = 2 t ck3 , dqs cas latency = 3 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop (burst length = 4, cas latency = 2, 3) dqm high for cas latency = 2 only. required to mask first bit of read data.
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 13 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c non-minimum read to write interval command nop nop read a write a nop nop nop dqm din a 0 din a 1 din a 2 din a 3 din a 0 din a 1 din a 2 din a 3 t ck2 , dqs cas latency = 2 t ck3 , dqs cas latency = 3 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop cl = 3: dqm needed to mask first bit of read data. cl = 2: dqm needed to mask first, second bit of read data. (burst length = 4, cas latency = 2, 3) : dqm high for cas latency = 2 : dqm high for cas latency = 3
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 14 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. burst write command the burst write command is initiated by having cs , cas , and we low while holding ras high at the rising edge of the clock. the address inputs determine the starting column address. there is no cas latency required for burst write cycles. data for the first burst write cycle must be applied on the dq pins on the sa me clock cycle that the write co mmand is issued. the remaining data inputs must be supplied on each subsequent rising clock ed ge until the burst length is comp leted. when the burst has fin- ished, any additional data supplied to the dq pins will be ignored. write interrupted by a write a burst write may be interrupted before completion of the burst by another write command. when the previous burst is inter- rupted, the remaining addresses are overridden by the new addres s and data will be written into the device until the pro- grammed burst length is satisfied. burst write operation write interrupted by a write command nop write a nop nop nop nop nop nop dqs din a 0 din a 1 din a 2 din a 3 nop ck t0 t2 t1 t3 t4 t5 t6 t7 t8 extra data is masked. the first data element and the write are registered on the same clock edge. ( burst length = 4, cas latency = 2, 3) : ?h? or ?l? command nop write a write b nop nop nop nop nop dqs din a 0 din b 0 din b 1 din b 2 nop din b 3 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 1 ck interval (burst length = 4, cas latency = 2, 3)
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 15 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c write interrupted by a read a read command will inte rrupt a burst write operation on the same clock cycle that the read command is registered. the dqs must be in the high impedance state at least one cycle before the interrupting read data appears on the outputs to avoid data contention. when the read comma nd is registered, any re sidual data from the burst write cycl e will be ignored. da ta that is pre - sented on the dq pins befor e the read command is initiated will actually be written to the memory. minimum write to read interval command nop write a read b nop nop nop nop nop nop t ck2 , dqs cas latency = 2 din a 0 t ck3 , dqs cas latency = 3 din a 0 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 input data for the write is masked. input data must be removed from the dqs at least one clock cycle before the read data appears on the outputs to avoid data contention. dout b 0 dout b 1 dout b 2 dout b 3 dout b 0 dout b 1 dout b 2 dout b 3 (burst length = 4, cas latency = 2, 3) : ?h? or ?l?
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 16 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. non-minimum write to read interval command write a read b nop nop nop nop nop nop t ck2 , dqs cas latency = 2 din a 0 t ck3 , dqs cas latency = 3 din a 0 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 input data for the write is masked. input data must be removed from the dqs at least one clock cycle before the read data appears on the outputs to avoid data contention. dout b 0 dout b 1 dout b 2 dout b 3 dout b 0 dout b 1 dout b 2 dout b 3 nop din a 1 din a 1 (burst length = 4, cas latency = 2, 3) : ?h? or ?l?
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 17 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c auto-precharge operation before a new row in an active bank can be opened, the active bank must be precharged using either the precharge command or the auto-precharge function. when a read or a write command is given to the sdram, the cas timing accepts one extra address, column address a10, to allow the active bank to automa tically begin precharge at the earliest possible moment during the burst read or write cycle. if a10 is low when the read or wr ite command is issued, then no rmal read or write burst opera- tion is executed and the bank remains active at the completion of the burst sequence. if a10 is high when the read or write command is issued, then the auto-precharge function is e ngaged. during auto-precharge, a read command will execute as normal with the exception that the active bank will begin to pr echarge before all burst read cycles have been completed. regardless of burst length, the precharge will begin (cas latency - 1) clocks prior to the last data output. auto-precharge can also be implemented during write commands. a read or write command without auto-precharge can be terminated in the midst of a burst operation. however, a read or write command with auto-precharge cannot be interrupted by a co mmand to the same bank. theref ore use of a read, write, or precharge command to the same bank is prohibited during a read or write cycle with auto-prechar ge until the entire burst oper- ation is completed. once the precharge operation has star ted the bank cannot be reactivated until the precharge time (t rp ) has been satisfied. when using the auto-precharge command, the interval between the bank activate command and the beginning of the internal precharge operation must satisfy t ras(min) . if this interval does not satisfy t ras(min) then t rcd must be extended. burst read with auto-precharge command nop nop nop nop read a auto-precharge t rp ? ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop nop t rp ? * * t ck2 , dqs cas latency = 2 t ck3 , dqs cas latency = 3 begin auto-precharge * bank can be reactivated at completion of t rp . dout a 0 dout a 0 nop ? t rp is a function of clock cycle time and speed sort. see the clock frequency and latency table. (burst length = 1, cas latency = 2, 3)
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 18 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. burst read with auto-precharge burst read with auto-precharge command nop nop nop nop read a auto-precharge t rp ? ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop nop t rp ? * * t ck2 , dqs cas latency = 2 t ck3 , dqs cas latency = 3 begin auto-precharge dout a 0 dout a 0 nop dout a 1 dout a 1 * bank can be reactivated at completion of t rp . ? t rp is a function of clock cycle time and speed sort. see the clock frequency and latency table. (burst length = 2, cas latency = 2, 3) command nop nop nop nop read a auto-precharge t rp ? ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop nop t rp ? * * t ck2 , dqs cas latency = 2 t ck3 , dqs cas latency = 3 begin auto-precharge dout a 0 dout a 1 dout a 2 dout a 3 nop dout a 0 dout a 1 dout a 2 dout a 3 * bank can be reactivated at completion of t rp . ? t rp is a function of clock cycle time and speed sort. see the clock frequency and latency table. (burst length = 4, cas latency = 2, 3)
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 19 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c although a read command with auto-precharge can not be interrupted by a command to the same bank, it can be interrupted by a read or write command to a different bank. if the command is issued before auto-precharge begins then the precharge function will begin with the new command. the bank bei ng auto-precharged may be reactivated after the delay t rp . if interrupting a read command with auto-precharge with a wr ite command, dqm must be us ed to avoid dq contention. burst read with auto-prech arge interrupted by read burst read with auto-prech arge interrupted by write t rp ? command nop nop nop nop read a auto-precharge ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop t rp ? t ck2 , dqs cas latency = 2 t ck3 , dqs cas latency = 3 * bank can be reactivated at completion of t rp . dout a 0 dout a 1 nop dout a 0 dout a 1 dout b 0 dout b 1 read b dout b 2 dout b 3 dout b 0 dout b 1 dout b 2 dout b 3 ? t rp is a function of clock cycle time and speed sort. see the clock frequency and latency table. * * (burst length = 4, cas latency = 2, 3) command nop nop nop read a auto-precharge t rp ? ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop t ck2, dqs cas latency = 2 dqm nop dout a 0 din b 0 din b 1 write b din b 2 din b 3 nop din b 4 * bank can be reactivated at completion of t rp . ? t rp is a function of clock cycle time and speed sort. . see the clock frequency and latency table . * (burst length = 8, cas latency = 2)
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 20 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. if a10 is high when a write command is issued, the write with auto-precharge function is initia ted. the bank undergoing auto- precharge cannot be reactivated until t dal , data-in to active delay, is satisfied. similar to the read command, a write command with auto-prechar ge can not be interrupted by a command to the same bank. it can be interrupted by a read or write command to a diffe rent bank, however. the interrupting command will terminate the write. the bank undergoing auto-prec harge can not be reactivated until t dal is satisfied. burst write with auto-precharge burst write with auto-prech arge interrupted by write din a 0 command nop nop nop nop write a auto-precharge din a 1 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop din a 0 din a 1 t ck2 , dqs cas latency = 2 t ck3 , dqs cas latency = 3 nop nop nop * bank can be reactivated at completion of t dal . t dal ? t dal ? * * (burst length = 2, cas latency = 2, 3) see the clock frequency and latency table. ? t dal is a function of clock cycle time and speed sort. din a 0 command nop nop nop write a auto-precharge din a 1 t dal ? ck t0 t1 t2 t3 t4 t5 nop t ck3, dqs cas latency = 3 write b din b 0 din b 1 din b 2 din b 3 t6 t7 t8 nop nop nop * bank can be reactivated at completion of t dal . * (burst length = 4, cas latency = 3) see the clock frequency and latency table. ? t dal is a function of clock cy cle time and speed sort.
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 21 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c precharge command the precharge command is used to precharge or close a bank that has been activated. the precharge command is triggered when cs , ras , and we are low and cas is high at the rising edge of the clock. the precharge command can be used to pre- charge each bank separately or all banks simultaneously. th ree address bits, a10, ba0, and ba1, are used to define which bank(s) is to be precharged when the command is issued. for read cycles, the precharge command may be applied (cas latency - 1) prior to the last data output. for write cycles, a delay must be satisfied from the start of the last burst write cycle until the prechar ge command can be issu ed. this delay is known as t dpl , data-in to precharge delay. after the precharge command is issued, the precharged bank mu st be reactivated before a ne w read or write access can be executed. the delay between the precharge command and the activate command must be greater than or equal to the pre- charge time (t rp ). burst write with auto-prech arge interrupted by read bank selection for prec harge by address bits a10 bank select precharged bank(s) low ba0, ba1 single bank defined by ba0, ba1 high don?t care all banks din a 0 command nop nop nop write a auto-precharge din a 1 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop nop * t ck3 , dqs cas latency = 3 bank a can be reactivated at completion of t dal . * read b din a 2 nop dout b 0 dout b 1 dout b 2 t dal ? (burst length = 4, cas latency = 3) see the clock frequency and latency table. ? t dal is a function of clock cycle time and speed sort.
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 22 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. burst read followed by the precharge command burst write followed by the precharge command command read ax 0 nop nop nop nop nop nop nop t ck2 , dqs cas latency = 3 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 dout ax 0 dout ax 1 dout ax 2 dout ax 3 precharge a t rp bank a can be reactivated at completion of t rp . * * (burst length = 4, cas latency = 3) ? ? t rp is a function of clock cycle and speed sort. command nop nop nop write ax 0 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop nop din ax 0 din ax 1 bank can be reactivated at completion of t rp . * activate bank ax t ck2, dqs cas latency = 2 t dpl ? * t rp ? precharge a ? t dpl and t rp are functions of clock cycle and speed sort. see the clock frequency and latency table. (burst length = 2, cas latency = 2)
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 23 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c precharge termination the precharge command may be used to terminate either a burst re ad or burst write operation. when the precharge command is issued, the burst operation is termi nated and bank precharge begins. for burst read operations, valid data will continue to appear on the data bus as a function of cas latency. burst read interrupted by precharge command read ax 0 nop nop nop nop nop nop nop t ck2 , dqs cas latency = 2 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 dout ax 0 dout ax 1 dout ax 2 dout ax 3 precharge a t ck3 , dqs cas latency = 3 dout ax 0 dout ax 1 dout ax 2 dout ax 3 t rp ? t rp ? * * bank a can be reactivated at completion of t rp . * see the clock frequency and latency table. (burst length = 8, cas latency = 2, 3) ? t rp is a function of clock cy cle time and speed sort.
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 24 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. burst write operations will be terminated by the precharge command . the last write data that will be properly stored in the device is that write data that is presented to the device a nu mber of clock cycles prior to the precharge command equal to the data-in to precharge delay, t dpl . precharge termination of a burst write command nop nop nop write ax 0 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop nop din ax 1 din ax 2 t dpl ? din ax 0 t ck2 , dqs cas latency = 2 nop din ax 1 din ax 2 din ax 0 t ck3 , dqs cas latency = 3 dqm precharge a ? t dpl is an asynchronous timing and may be completed in one or two clock cycles depending on clock cycle time. (burst length = 8, cas latency = 2, 3) t dpl ?
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 25 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c automatic refresh command (cas before ras refresh) when cs , ras , and cas are held low with cke and we high at the rising edge of the clock, the chip enters the automatic refresh mode (cbr). all banks of the sdram must be precha rged and idle for a minimum of the precharge time (t rp ) before the auto refresh command (cbr) can be applied. an address counter, internal to the device provides the address during the refresh cycle. no control of th e external address pins is re quired once this cycle has started. when the refresh cycle has comple ted, all banks of th e sdram will be in the pr echarged (idle) state. a delay betwe en the auto refresh command (cbr) and the next activate command or subsequent auto refresh comm and must be greater than or equal to the ras cycle time (t rc ). self refresh command the sdram device has a built-in timer to accommodate self re fresh operation. the self refresh command is defined by hav- ing cs , ras , cas , and cke held low with we high at the rising edge of the clock. all banks must be idle prior to issuing the self refresh command. once the command is registered, cke mu st be held low to keep the device in self refresh mode. when the sdram has entered self refresh mo de all of the external control signals, except cke, are disabled. the clock is internally disabled during self refresh operat ion to save power. the user may halt the external clock while the device is in se lf refresh mode, however, the clock must be restarted before the device can exit self refresh operation. once the clock is cycling, the device will exit self refresh operation after cke is returned high. a minimum delay time is required when the devi ce exits self refresh operation and bef ore the next command can be issued. this delay is equal to the ras cycle time (t rc ) plus the self refresh exit time (t srex ).
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 26 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. power down mode in order to reduce standby power consumption, two power do wn modes are available: precharge and active power down mode. to enter precharge power down mode, all banks mu st be precharged and the necessary precharge delay (t rp ) must occur before the sdram can enter the power down mode. if a b ank is activated but not perfo rming a read or write operation, active power down mode will be entered. (issuing a power down mode command when the device is performing a read or write operation causes the device to enter clock suspend mode. see the following clock suspend section.) once the power down mode is initiated by holding cke low, all of the receiver circuits except cke are gated off. the power down mode does not perform any refresh operations, ther efore the device can?t remain in power down mode longer than the refresh period (t ref ) of the device. the power down mode is exited by bringing cke high. when cke goes high, a no operation command (or device deselect command) is required on the next rising clock edge. power down mode exit timing command nop command nop nop nop nop nop cke : ?h? or ?l? ck tm tm+2 tm+1 tm+3 tm+4 tm+5 tm+6 tm+7 tm+ 8 t ces(min) t ck
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 27 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c data mask the sdram has a data mask function that can be used in conjunc tion with data read and write cycles. when the data mask is activated (dqm high) during a write cycle, the write operation is prohibited immediately (zero clock latency). if the data mask is activated during a read cycle, the data outputs are disabled and become high impedance after a two-clock delay, independent of cas latency. no operation command the no operation command should be used in cases when the sd ram is in an idle or a wait state. the purpose of the no operation command is to prevent the s dram from registering any unwanted command s between operations. a no operation command is registered when cs is low with ras , cas , and we held high at the rising edge of the clock. a no operation com- mand will not terminate a previous ope ration that is still ex ecuting, such as a burst read or write cycle. deselect command the deselect command performs the same function as a no operation command. deselect command occurs when cs is brought high, the ras , cas , and we signals become don?t cares. data mask activated during a read cycle command nop read a nop nop nop nop nop nop nop dqm : ?h? or ?l? a two-clock delay before the dqs become hi-z dqs ck t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 0 dout a 1 (burst length = 4, cas latency = 2)
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 28 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. clock suspend mode during normal access mode, cke is held high, enabling the clock. when cke is registered low while at least one of the banks is active, clock suspend mode is entered. the clock suspend mode deactivates the internal clock and suspends or ?freezes? any clocked operation that was currently being executed. there is a one-clock dela y between the registration of cke low and the time at which the sdram?s operation suspends. while in clock suspend mode, the sdram ignores any new commands that are issued. the clock suspend mode is exited by bringing cke high. there is a one clock cycle delay from when cke returns high to when clock suspend mode is exited. when the operation of the sdram is suspended during the execution of a burst read operation, the last valid data output onto the dq pins will be actively held valid until clock suspend mode is exited. if clock suspend mode is initiated during a burst write operati on, the input data is masked and is ignored until the clock sus- pend mode is exited. clock suspend durin g a read cycle clock suspend during a write cycle ck t0 t2 t1 t3 t4 t5 t6 t7 t8 command nop read a nop nop nop nop cke dqs dout a 0 dout a 2 dout a 1 : ?h? or ?l? a one clock delay before suspend operation starts a one clock delay to exit the suspend command dout element at the dqs when the suspend operation starts is held valid (burst length = 4, cas latency = 2) ck t0 t2 t1 t3 t4 t5 t6 t7 t8 command nop write a nop nop nop nop cke dqs din a 2 din a 3 : ?h? or ?l? a one clock delay before suspend operation starts a one clock delay to exit the suspend command din is masked during the clock suspend period din a 1 din a 0 (burst length = 4, cas latency = 2)
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 29 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c command truth table (see note 1) function device state cke cs ras cas we dqm ba0, ba1 a10 a12, a11, a9-a0 notes previous cycle current cycle mode register set idle h x l l l l x op code auto (cbr) refresh idle h h l l l h x x x x entry self refresh idle h l l l l h x x x x exit self refresh idle (self- refresh) lh hxxx xxx x lhhh single bank precharge see current state table hxllhlxbslx2 precharge all banks see current state table hxllhlxxhx bank activate idle h x l l h h x bs row address 2 write active h x l h l l x bs l column 2 write with auto-precharge active h x l h l l x bs h column 2 read active h x l h l h x bs l column 2 read with auto-precharge active h x l h l h x bs h column 2 burst stop active h x l h h l x x x x no operation any h x l h h h x x x x device deselect any h x h x x x x x x x clock suspend mode entry active h l x x x x x x x x 4 clock suspend mode exit active l h x x x x x x x x data write/output enable active h x x x x x l x x x 5 data mask/output disable active h x x x x x h x x x power down mode entry idle/active h l hxxx xxx x6, 7 lhhh power down mode exit any (power down) lh hxxx xxx x6, 7 lhhh 1. all of the sdram operations are defined by states of cs , we , ras , cas , and dqm at the positive rising edge of the clock. refer to the current state truth table. 2. bank select (ba0, ba1): ba0, ba1 = 0,0 selects bank 0; ba0, ba1 = 1,0 selects bank 1; ba0, ba1 = 0,1 selects bank 2; ba0, ba1 = 1,1 selects bank 3. 3. not applicable. 4. during normal access mode, cke is held high and ck is enabled. when it is low, it freezes the internal clock and extends data read and write operations. one cl ock delay is required for mode entry and exit. 5. the dqm has two functions for the data dq read and write opera tions. during a read cycle, when dq m goes high at a clock timin g the data outputs are disabled and become high impedance after a two-clock delay. dqm also provides a data mask function for write c ycles. when it activates, the write operation at t he clock is prohibited (zero clock latency). 6. all banks must be precharged before entering the power down mode. (if this command is issued during a burst operation, the de vice state will be clock suspend mode.) the power down mode does not perform any refresh operations; t herefore the device can?t rema in in this mode longer than the refresh period (t ref ) of the device. one clock delay is required for mode entry and exit. 7. a no operation or device deselect command is requi red on the next clock edge following cke going high.
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 30 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. clock enable (cke) truth table current state cke command action notes previous cycle current cycle cs ras cas we ba0, ba1 a12 - a0 self refresh h x xxxx x xinvalid 1 l h h x x x x x exit self refresh with device deselect 2 l h l h h h x x exit self refresh with no operation 2 l h l h h l x x illegal 2 l h l h l x x x illegal 2 l h l l x x x x illegal 2 l l xxxx x xmaintain self refresh power down h x xxxx x xinvalid 1 l h h x x x x x power down mode exit, all banks idle 2 l h lxxx x xillegal 2 l l xxxx x xmaintain power down mode all banks idle h h hxxx refer to the idle state section of the current state truth table 3 hhlhxx 3 hhllhx 3 h h lllh x xcbr refresh h h llll op codem ode register set 4 h l hxxx refer to the idle state section of the current state truth table 3 hllhxx 3 hlllhx 3 h l l l l h x x entry self refresh 4 h l llll op codem ode register set l x xxxx x xpower down 4 any state other than listed above h h xxxx x x refer to operations in the current state truth table h l xxxx x xbegin clock suspend next cycle 5 l h xxxx x xexit clock sus pend next cycle l l xxxx x xmaintain clock sus pend 1. for the given current state cke must be low in the previous cycle. 2. when cke has a low to high transition, the clock and other inpu ts are re-enabled asynchronously. the minimum setup time for c ke (t ces ) must be satisfied. when exiting power down mode, a nop command (or device deselect command) is required on the first rising clock after cke goes high (see page 26). 3. the address inputs depend on the command that is issued. see the idle state section of the current state truth table for more informa- tion. 4. the precharge power down mode, the self refresh mode, and th e mode register set can only be entered from the all banks idle s tate. 5. must be a legal command as defined in the current state truth table.
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 31 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c current state truth table (part 1 of 3)(see note 1) current state command action notes cs ras cas we ba0,ba1 a12 - a0 description idle llll op code m ode register set set the mode register 2 l l l h x x auto or self refresh start auto or self refresh 2, 3 l l h l bs x precharge no operation l l h h bs row address bank activate activate the specified bank and row l h l l bs column write w/o precharge illegal 4 l h l h bs column read w/o precharge illegal 4 l h h l x x burst stop illegal l h h h x x no operation no operation h x x x x x device deselect no operation or power down 5 row active llll op code m ode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge precharge 6 l l h h bs row address bank activate illegal 4 l h l l bs column write start write; determine if auto precharge 7, 8 l h l h bs column read start read; determine if auto precharge 7, 8 l h h l x x burst stop illegal l h h h x x no operation no operation h x x x x x device deselect no operation read llll op code m ode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge terminate burst; start the precharge l l h h bs row address bank activate illegal 4 l h l l bs column write terminate burst; start the write cycle 8, 9 l h l h bs column read terminate burst; start a new read cycle 8, 9 l h h l x x burst stop burst stop l h h h x x no operation continue the burst h x x x x x device deselect continue the burst write llll op code m ode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge terminate burst; start the precharge l l h h bs row address bank activate illegal 4 l h l l bs column write terminate burst; start a new write cycle 8, 9 l h l h bs column read terminate burst; start the read cycle 8, 9 l h h l x x burst stop burst stop l h h h x x no operation continue the burst h x x x x x device deselect continue the burst 1. cke is assumed to be active (high) in t he previous cycle for all entries. the current state is the state of the bank that the command is being applied to. 2. all banks must be idle; other wise, it is an illegal action. 3. if cke is active (high) the sdram will start the auto (cbr) re fresh operation, if cke is inactive (low) than the self refresh mode is entered. 4. the current state refers to only one of the banks. if bs selects this bank then the action is illegal. if bs selects the bank not being refer- enced by the current state then the action may be legal depending on the state of that bank. 5. if cke is inactive (low) then the power down mode is entered; otherwise there is a no operation. 6. the minimum and maximum active time (t ras ) must be satisfied. 7. the ras to cas delay (t rcd ) must occur before the command is given. 8. column address a10 is used to determine if the auto precharge function is activated. 9. the command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. the command is illegal if the minimum bank to bank delay time (t rrd ) is not satisfied.
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 32 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. read with auto pre- charge llll op code m ode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal 4 l l h h bs row address bank activate illegal 4 l h l l bs column write illegal 4 lhlh bs columnread illegal 4 l h h l x x burst stop illegal l h h h x x no operation continue the burst h x x x x x device deselect continue the burst write with auto precharge llll op code m ode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal 4 l l h h bs row address bank activate illegal 4 l h l l bs column write illegal 4 lhlh bs columnread illegal 4 l h h l x x burst stop illegal l h h h x x no operation continue the burst h x x x x x device deselect continue the burst precharging llll op code m ode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge no operation; bank(s) idle after t rp l l h h bs row address bank activate illegal 4 l h l l bs column write illegal 4 lhlh bs columnread illegal 4 l h h l x x burst stop illegal l h h h x x no operation no operation; bank(s) idle after t rp h x x x x x device deselect no operation; bank(s) idle after t rp row activating llll op code m ode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal 4 l l h h bs row address bank activate illegal 4, 10 l h l l bs column write illegal 4 lhlh bs columnread illegal 4 l h h l x x burst stop illegal l h h h x x no operation no operation; row active after t rcd h x x x x x device deselect no operation; row active after t rcd current state truth table (part 2 of 3)(see note 1) current state command action notes cs ras cas we ba0,ba1 a12 - a0 description 1. cke is assumed to be active (high) in t he previous cycle for all entries. the current state is the state of the bank that the command is being applied to. 2. all banks must be idle; other wise, it is an illegal action. 3. if cke is active (high) the sdram will start the auto (cbr) re fresh operation, if cke is inactive (low) than the self refresh mode is entered. 4. the current state refers to only one of the banks. if bs selects this bank then the action is illegal. if bs selects the bank not being refer- enced by the current state then the action may be legal depending on the state of that bank. 5. if cke is inactive (low) then the power down mode is entered; otherwise there is a no operation. 6. the minimum and maximum active time (t ras ) must be satisfied. 7. the ras to cas delay (t rcd ) must occur before the command is given. 8. column address a10 is used to determine if the auto precharge function is activated. 9. the command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. the command is illegal if the minimum bank to bank delay time (t rrd ) is not satisfied.
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 33 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c write recovering llll op code m ode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal 4 l l h h bs row address bank activate illegal 4 l h l l bs column write start write; determine if auto precharge 9 l h l h bs column read start read; determine if auto precharge 9 l h h h x x no operation no operation; row active after t dpl h x x x x x device deselect no operation; row active after t dpl write recovering with auto pre- charge llll op code m ode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal 4 l l h h bs row address bank activate illegal 4 l h l l bs column write illegal 4, 9 lhlh bs columnread illegal 4, 9 l h h h x x no operation no operation; precharge after t dpl h x x x x x device deselect no operation; precharge after t dpl refreshing llll op code m ode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal l l h h bs row address bank activate illegal l h l l bs column write illegal lhlh bs columnread illegal l h h h x x no operation no operation; idle after t rc h x x x x x device deselect no operation; idle after t rc mode register accessing llll op code m ode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal l l h h bs row address bank activate illegal l h l l bs column write illegal lhlh bs columnread illegal l h h h x x no operation no operation; idle after tw o clock cycles h x x x x x device deselect no operati on; idle after two clock cycles current state truth table (part 3 of 3)(see note 1) current state command action notes cs ras cas we ba0,ba1 a12 - a0 description 1. cke is assumed to be active (high) in t he previous cycle for all entries. the current state is the state of the bank that the command is being applied to. 2. all banks must be idle; other wise, it is an illegal action. 3. if cke is active (high) the sdram will start the auto (cbr) re fresh operation, if cke is inactive (low) than the self refresh mode is entered. 4. the current state refers to only one of the banks. if bs selects this bank then the action is illegal. if bs selects the bank not being refer- enced by the current state then the action may be legal depending on the state of that bank. 5. if cke is inactive (low) then the power down mode is entered; otherwise there is a no operation. 6. the minimum and maximum active time (t ras ) must be satisfied. 7. the ras to cas delay (t rcd ) must occur before the command is given. 8. column address a10 is used to determine if the auto precharge function is activated. 9. the command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. the command is illegal if the minimum bank to bank delay time (t rrd ) is not satisfied.
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 34 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. absolute maximum ratings symbol parameter rating units notes v dd power supply voltage -0.3 to +4.6 v 1 v ddq power supply voltage for output -0.3 to +4.6 v 1 v in input voltage -0.3 to v dd +0.3 v 1 v out output voltage -0.3 to v dd +0.3 v 1 t a operating temperature (ambient) -40 to +85 c1 t stg storage temperature -55 to +125 c1 p d power dissipation 1.0 w 1 i out short circuit output current 50 ma 1 1. stresses greater than those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stres s rat- ing only and functional operation of the device at these or any other conditions above those indicated in the operational secti ons of this specification is not implied. exposure to absolute maximum rating conditions fo r extended periods may affect reliability. recommended dc operating conditions (t a = -40 c to 85 c) symbol parameter rating units notes min. typ. max. v dd supply voltage 3.0 3.3 3.6 v 1 v ddq supply voltage for output 3.0 3.3 3.6 v 1 v ih input high voltage 2.0 ? v dd + 0.3 v 1, 2 v il input low voltage -0.3 ? 0.8 v 1, 3 1. all voltages referenced to v ss and v ssq . 2. v ih (max) = v dd + 1.2v for pulse width 5ns. 3. v il (min) = v ss - 1.2v for pulse width 5ns. capacitance (t a = 25 c, f = 1mhz, v dd = 3.3v 0.3v) symbol parameter min. typ max. units notes c i input capacitance (a0-a12, ba0, ba1, cs , ras , cas , we , cke, dqm) 2.5 3.0 3.8 pf input capacitance (ck) 2.5 2.8 3.5 pf c o output capacitance (dq0 - dq15) 4.0 4.5 6.5 pf
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 35 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c dc electrical characteristics (t a = -40 to +85 c, v dd = 3.3v 0.3v) symbol parameter min. max. units i i(l) input leakage current, any input (0.0v v in v dd ), all other pins not under test = 0v -1 +1 a i o(l) output leakage current (d out is disabled, 0.0v v out v ddq ) -1 +1 a v oh output level (lvttl) output ?h? level voltage ( iout = -2.0ma) 2.4 ? v v ol output level (lvttl) output ?l? level voltage (i out = +2.0ma) ?0.4 v dc output load circuit output 1200 ? 50pf 3.3 v 870 ? v oh (dc) = 2.4v, i oh = -2ma v ol (dc) = 0.4v, i ol = 2ma
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 36 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. operating, standby, and refresh currents (t a = -40 to +85 c, v dd = 3.3v 0.3v) parameter symbol test condition speed units notes -6k/6ki -75b/75bi operating current i cc1 1 bank operation t rc = t rc (min), t ck = min active-precharge command cycling without burst operation 100 95 ma 1, 2, 3 precharge standby current in power down mode i cc2p cke v il (max), t ck = min, cs = v ih (min) 44ma1 i cc2ps cke v il (max), t ck = infinity, cs = v ih (min) 44ma1 precharge standby current in non-power down mode i cc2n cke v ih (min), t ck = min, cs = v ih (min) 23 20 ma 1, 5 i cc2ns cke v ih (min), t ck = infinity, 12 10 ma 1, 7 no operating current (active state: 4 bank) i cc3n cke v ih (min), t ck = min, cs = v ih (min) 46 41 ma 1, 5 i cc3p cke v il (max), t ck = min, 7 5 ma 1, 6 operating current (burst mode) i cc4 t ck = min, read/ write command cycling, multiple banks active, gapless data, bl = 4 95 85 ma 1, 3, 4 auto (cbr) refresh current i cc5 t ck = min, t rc = t rc (min) cbr command cycling 186 156 ma 1 self refresh current i cc6 cke 0.2v 4 4 ma 1 1. currents given are valid for a single device. . 2. these parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t ck and t rc . input signals are changed up to three times during t rc (min). 3. the specified values are obtained with the output open. 4. input signals are changed once during t ck (min). 5. input signals are changed once during three clock cycles. 6. active standby current will be higher if clock suspe nd is entered during a burst read cycle (add 1ma per dq). 7. input signals are stable.
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 37 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c ac characteristics (t a = -40 to +85 c, v dd = 3.3v 0.3v) 1. an initial pause of 200 s, with dqm and cke held high, is required afte r power-up. a precharge all banks command must be given followed by a minimum of two auto (cbr) refresh cycles befor e or after the mode r egister set operation. 2. the transition time is measured between v ih and v il (or between v il and v ih ) 3. in addition to meeting the transition rate specif ication, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 4. load circuit a: ac timing tests have v il = 0.4 v and v ih = 2.4 v with the timing referenced to the 1.40v crossover point 5. load circuit a: ac measurements assume t t = 1.0ns. 6. load circuit b: ac timing tests have v il = 0.8 v and v ih = 2.0 v with the timing referenced to the 1.40v crossover point 7. load circuit b: ac measurements assume t t = 1.2ns. . ac characteristics diagrams output input clock t oh t setup t hold t ac t lz 1.4v 1.4v 1.4v t t vtt = 1.4v output 50 ? 50pf z o = 50 ? ac output load circuit (a) t ckh t ckl output 50pf z o = 50 ? ac output load circuit (b) v il v ih
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 38 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. clock and clock enable parameters symbol parameter -6k/6ki -75b/75bi units notes min. max. min. max. t ck3 clock cycle time, cas latency = 3 6.0 1000 7.5 1000 ns t ck2 clock cycle time, cas latency = 2 10 1000 10 1000 ns t ac3 (a) clock access time, cas latency = 3 ? ? ? ? ns 1 t ac2 (a) clock access time, cas latency = 2 ? ? ? ? ns 1 t ac3 (b) clock access time, cas latency = 3 ? 5 ? 5.4 ns 2 t ac2 (b) clock access time, cas latency = 2 ? 5.4 ? 6 ns 2 t ckh clock high pulse width 2 ? 2.5 ? ns t ckl clock low pulse width 2 ? 2.5 ? ns t ces clock enable set-up time 1.5 ? 1.5 ? ns t ceh clock enable hold time 0.8 ? 0.8 ? ns t sb power down mode entry time 0 6 0 7.5 ns t t transition time (rise and fall) 0.3 8 0.5 10 ns 1. access time is measured at 1.4v . see ac characteristics: notes 1, 2, 3, 4, 5 and load circuit a. 2. access time is measured at 1.4v. see ac charac teristics: notes 1, 2, 3, 6, 7 and load circuit b. common parameters symbol parameter -6k/6ki -75b/75bi units notes min. max. min. max. t cs command setup time 1.5 ? 1.5 ? ns t ch command hold time 0.8 ? 0.8 ? ns t as address and bank select set-up time 1.5 ? 1.5 ? ns t ah address and bank select hold time 0.8 ? 0.8 ? ns t rcd ras to cas delay 16 ? 20 ? ns 1 t rc bank cycle time 54 ? 67.5 ? ns 1 t ras active command period 36 100k 45 100k ns 1 t rp precharge time 16 ? 20 ? ns 1 t rrd bank to bank delay time 12 ? 15 ? ns 1 t ccd cas to cas delay time 1?1? ck 1. these parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of ti ming / clock period (count fr actions as a whole number). mode register set cycle symbol parameter -6k/6ki -75b/75bi units min. max. min. max. t rsc mode register set cycle time 12 ? 15 ? ns
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 39 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c read cycle symbol parameter -6k/6ki -75b/75bi units notes min. max. min. max. t oh data out hold time ????ns1 2.5 ? 2.7 ? ns 2, 4 t lz data out to low impedance time 0 ? 0 ? ns t hz data out to high impedance time 3637ns3 t dqz dqm data out disable latency 2 ? 2 ? ck 1. ac output load circuit a. 2. ac output load circuit b. 3. referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. 4. data out hold time with no load must meet 1.8ns (-75h, -75d, -75a). refresh cycle symbol parameter -6k/6ki -75b/75bi units notes min. max. min. max. t ref refresh period ? 64 ? 64 ms 1 t srex self refresh exit time 1 ? 1 ? ck 1. 8192 auto refresh cycles. write cycle symbol parameter -6k6ki -75b/75bi units min. max. min. max. t ds data in set-up time 1.5 ? 1.5 ? ns t dh data in hold time 0.8 ? 0.8 ? ns t dpl data input to precharge 12 ? 15 ? ns t wr write recovery time 12 ? 15 ? ns t dal3 data in to active delay cas latency = 3 5?5? ck t dal2 data in to active delay cas latency = 2 4?4? ck t dqw dqm write mask latency 0 ? 0 ? ck
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 40 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. clock frequency and latency symbol parameter -6k/6ki -75b/75bi units f ck clock frequency 166 133 mhz t ck clock cycle time 6.0 7.5 ns t aa cas latency 3 3 ck t rp precharge time 3 3 ck t rcd ras to cas delay 3 3 ck t rc bank cycle time 9 9 ck t ras minimum bank active time 6 6 ck t dpl data in to precharge 2 2 ck t dal data in to active/refresh 5 5 ck t rrd bank to bank delay time 2 2 ck t ccd cas to cas delay time 1 1 ck t wl write latency 0 0 ck t dqw dqm write mask latency 0 0 ck t dqz dqm data disable latency 2 2 ck t csl clock suspend latency 1 1 ck
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 41 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c ac parameters for write timing \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, t ces t cs t ch t as t rcd t dal ? t ds activate command bank 0 write with auto precharge command bank 0 activate command bank 1 write with auto precharge command bank 1 activate command bank 0 write command bank 0 precharge command bank 0 activate command bank 0 t dh ax0 ax3 ax2 ax1 bx0 bx3 bx2 bx1 ay0 ay3 ay2 ay1 t ck2 t ckh t ckl activate command bank 1 ray cbx cay ray rbx rbx cax rby rby raz raz rax rax t ah * ba0 = ?l? bank2,3 = idle t rc t ceh t dpl ? t rp t rrd t dpl and t dal depend on clock cycle time and (burst length = 4, cas latency = 2) ? speed sort. see the clock frequency and latency table. a11,a12
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 42 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. ac parameters for read timing (3/3/3) \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t10 hi-z a10 a0-a9, t rcd t ras activate command bank 0 activate command bank 1 activate command bank 0 t ck3 read with auto precharge command bank 1 t rc t ac3 t oh bx0 bx1 cbx ray rbx rbx ray cax rax rax * ba0 = ?l? read with auto precharge command bank 0 begin auto precharge bank 0 bank2,3 = idle t rp bx2 begin auto precharge bank 1 t rrd ax3 ax2 ax1 ax0 (burst length = 4, cas latency = 3; t rcd , t rp = 3) a11, a12
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 43 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c ac parameters for r ead timing (2/2/2) \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t10 hi-z a10 t cs t ch t ceh t as t ah t rrd t rcd t ras(min) t lz activate command bank 0 activate command bank 1 activate command bank 0 t ces t ck2 read with auto precharge command bank 1 t rc t rp t ac2 t oh t hz t ckh bx0 begin auto precharge bank 1 bx1 t hz cbx ray rbx rbx ray cax rax rax t ckl ax0 ax1 * ba0 = ?l? read with auto precharge command bank 0 begin auto precharge bank 0 bank2,3 = idle t rp note: must satisfy t ras(min) for -260: extend t rcd 1 clock (burst length = 2, cas latency = 2; t rcd , t rp = 2) a0-a9, a11, a12
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 44 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. ac parameters for read timing (3/2/2) \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t10 hi-z a10 t cs t ch t ceh t as t ah t rcd t lz activate command bank 0 activate command bank 1 activate command bank 0 t ck3 read with auto precharge command bank 1 t rp t ac3 t oh t hz t ckh bx0 begin auto precharge bank 1 bx1 t hz cbx ray rbx rbx ray cax rax rax t ckl ax0 ax1 * ba0=? l? read with auto precharge command bank 0 begin auto precharge bank 0 bank2,3=idle t rp t ces note: must satisfy t ras(min). extended t rcd 1 clock. not required for bl 4. t rrd t ras t rc (burst length = 2, cas latency = 3; t rcd , t rp = 2) a0-a9, a11, a12
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 45 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c ac parameters for read timing (3/3/3) \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t10 hi-z a10 a0-a9, t rrd t rcd t ras (min) activate command bank 0 activate command bank 1 activate command bank 0 t ck3 read with auto precharge command bank 1 t rc t rp t ac3 t oh bx0 begin auto precharge bank 1 bx1 cbx ray rbx rbx ray cax rax rax read with auto precharge command bank 0 begin auto precharge bank 0 t rp ax0 ax1 note: must satisfy t ras (min). extended t rcd not required for bl 4. t ceh a11, a12 t14 * ba0=? l? bank 2,3=idle (burst length = 2, cas latency = 3; t rcd , t rp = 3)
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 46 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. mode register set \ ck cke cs dq ras cas we ba0,ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10,a11, a0-a9 precharge command all banks mode register set command any command address key t rp t ck2 t rsc (cas latency = 2) a12
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 47 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c power-on sequence and auto refresh (cbr) \ ck cke cs dq ras cas we bs dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, precharge command all banks t rp minimum of 8 refresh cycles are required 1st auto refresh command t rc high level is required 8th auto refresh command inputs must be stable for 200 s t ck any command 2 clock min. mode register address key set command a11,a12
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 48 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. clock suspension / dqm during burst read \ ck cke cs dq ras cas we dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, rax ax0 ax1 ax2 ax3 activate command bank 0 clock suspend 2 cycles clock suspend 1 cycle clock suspend 3 cycles rax read command bank 0 cax t hz t ck3 * ba1 ax4 ax6 ax7 t ces t ceh * ba0=? l? bank2,3=idle (burst length = 8, cas latency = 3; t rcd = 3) a11,a12
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 49 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c clock suspension / dqm during burst write \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, rax activate command bank 0 rax cax dax0 clock suspend 1 cycle dax1 dax2 clock suspend 2 cycles clock suspend 3 cycles write command bank 0 t ck3 dax5 dax6 dax7 dax3 * ba0=? l? bank2,3=idle (burst length = 8, cas latency = 3; t rcd = 3) a11, a12
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 50 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. power down mode and clock suspend \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0 -a9, t ces t ces valid cax rax rax ax2 ax0 ax1 ax3 activate command bank 0 nop read command bank 0 active standby clock suspension start clock suspension end precharge command bank 0 precharge standby t hz any command t ck2 t ces t sb nop * ba0=? l? bank2,3=idle t sb (burst length = 4, cas latency = 2) a11,a12
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 51 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c auto refresh (cbr) \ ck cke cs dq ras cas we bs dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, precharge command auto refresh command auto refresh command t rc t rp t rc t ck2 all banks (cas latency = 2) a11,a12
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 52 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. self refresh (e ntry and exit) \ ck cke cs dq ras cas we bs dqm t2 t3 t4 t0 t1 hi-z a10 all banks must be idle self refresh entry a0-a9, tm tm+2 tm+3 tm+4 tm+5 tm+1 tm+7 tm+8 tm+9 tm+10 tm+6 tm+13 tm+11 tm+12 tm+15 tm+14 t ces t sb any command t ces t rc t srex self refresh exit power down entry power down exit (note: the ck signal must be reestablished prior to cke returning high.) a11,a12
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 53 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c random row read (interleavi ng banks) with precharge \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, cby read command bank 1 by0 t ck3 high t ac3 activate command bank 1 rbx rbx activate command bank 0 rax rax cbx read command bank 1 activate command bank 1 rby rby t rcd precharge command bank 1 cax read command bank 0 bx0 bx1 bx2 bx3 bx4 bx5 bx6 ax0 ax1 ax4 ax5 ax6 ax7 precharge command bank 0 * ba0=? l? bank2,3=idle (burst length = 8, cas latency = 3; t rcd , t rp = 3) a11,a12
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 54 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. random row read (interleaving ba nks) with auto-precharge \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, cby by0 t ck3 high t ac3 activate command bank 1 rbx rbx activate command bank 0 rax rax cbx activate command bank 1 rby rby t rcd cax bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 ax0 ax4 ax5 ax6 read with auto precharge command bank 1 ax1 start auto precharge bank 1 read with auto precharge command bank 0 start auto precharge bank 0 read with auto precharge command bank 1 * ba0=? l? bank2,3=idle rax rax ax7 (burst length = 8, cas latency = 3; t rcd , t rp = 3) a11,a12
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 55 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c random row write (interleaving banks) with auto-precharge \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, t ck3 high dax0 dax1 dax4 dax7 dax6 dax5 dbx0 dbx3 dbx2 dbx1 dbx4 dbx5 day2 day1 day0 cax activate command bank 0 rax rax activate command bank 1 rbx rbx activate command bank 0 ray ray cbx cay t rcd dbx7 dbx6 write with auto precharge command bank 0 write with auto precharge command bank 1 write with auto precharge command bank 0 * ba0=? l? bank2,3=idle t dal ? t dal ? ? number of clocks depends on clock cycle time and speed sort. see the clock frequency and latency table. bank may be reactivated at the completion of t dal . (burst length = 8, cas latency = 3; t rcd , t rp = 3) a11,a12
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 56 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. random row write (interleavi ng banks) with precharge \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, t ck3 high dax0 dax1 dax4 dax7 dax6 dax5 dbx0 dbx3 dbx2 dbx1 dbx4 dbx5 day2 day1 day0 write command bank 0 cax activate command bank 0 rax rax activate command bank 1 rbx rbx activate command bank 0 ray ray cbx write command bank 1 precharge command bank 0 write command bank 0 cay precharge command bank 1 t rp t rcd dbx7 dbx6 * ba0=? l? bank2,3=idle (burst length = 8, cas latency = 3; t rcd , t rp = 3) t dpl a11,a12
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 57 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c read / write cycle \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, t ck3 write command bank 0 cay day0 day1 day3 ax0 ax1 ax3 ax2 the write data is masked with a zero clock latency the read data is masked with a two clock latency activate command bank0 rax rax cax read command bank 0 day4 precharge command bank 0 * ba0=? l? bank2,3=idle (burst length = 8, cas latency = 3; t rcd , t rp = 3) a11,a12
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 58 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. interleaved column read cycle \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, t ck3 t rcd t ac3 cby read command bank 1 cbz read command bank 1 cay precharge command bank 1 ax0 ax3 ax2 ax1 bx0 by1 by0 bx1 bz0 bz1 ay0 ay3 ay2 ay1 activate command bank 0 rax rax cbx read command bank 1 cax activate command bank 1 read command bank 0 rbx rbx read with auto precharge command bank 0 start auto precharge bank 0 * ba0=? l? bank2,3=idle (burst length = 4, cas latency = 3; t rcd , t rp = 3) a11,a12
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 59 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c auto precharge after read burst \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, t ck3 high read with auto precharge command bank 1 cby start auto precharge bank 1 start auto precharge bank 0 ax3 ax2 ax0 ax1 bx3 bx2 bx0 bx1 ay3 ay2 ay0 ay1 activate command bank 0 rax rax read with auto precharge command bank 1 cbx read with auto precharge command bank 0 activate command bank 1 rbx cax rbx activate command bank 1 read command bank 0 rby cay rby by0 by1 * ba0=? l? bank2,3=idle start bank 1 auto precharge (burst length = 4, cas latency = 3; t rcd , t rp = 3) a11,a12
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 60 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. auto precharge after write burst \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, t ck2 high write with auto precharge command bank 1 cby activate command bank 1 rbx rbx write with auto precharge command bank 1 cbx dax3 dax2 dax1 dax0 dbx3 dbx2 dbx1 dbx0 day3 day2 day1 day0 dby3 dby2 dby1 dby0 daz3 daz2 daz1 daz0 activate command bank 0 raz raz write command bank 0 cax write with auto precharge command bank 0 cay activate command bank 1 rby rby activate command bank 0 rax rax write with auto precharge command bank 0 caz * ba0=? l? bank2,3=idle a11,a12 t dal ? t dal ? ? number of clocks depends on clock cycle and speed sort. see the clock frequency and latency table. bank may be reactivated at the completion of t dal . t dal ? (burst length = 4, cas latency = 2)
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 61 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c burst read and single write operation \ ck cke cs dq 0 - dq 7 ras cas we * ba1 ldqm a10 a0-a9, dq 8 - dq 15 udqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z t ck2 activate command bank 0 rav rav cav read command bank 0 single write command bank 0 caw high cay read command bank 0 av0 daw0 hi-z av2 av1 av3 dax0 av2 av1 ay2 daw0 ay0 ay3 av0 av3 single write command bank 0 ay3 single write command bank 0 daz0 daz0 cax caz lower byte is masked ay0 ay1 upper byte is masked lower byte is masked * ba0=? l? bank2,3=idle (burst length = 4, cas latency = 2) a11, a12
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 62 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. cs function (only cs signal needs to be asserted at minimum rate) \ ck cke cs dq ras cas we ba0,ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10, a12 a0-a9, a11 t ck3 rax low rax cax cay read command bank a write command bank a activate command bank a precharge command bank a ax0 day0 day3 day2 day1 ax3 ax2 ax1 t rcd t dpl (at 100mhz burst length = 4, cas latency = 3, t rcd , t rp = 3)
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 63 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c package dimensions (400mil; 54 lead; thin small outline package) lead #1 0.80 basic 0.35 10.16 0.13 22.22 0.13 11.76 0.20 - 0.05 + 0.10 0.71ref detail a 0.10 0.05 seating plane detail a 0.5 0.1 0.05 min 1.20 max 0.25 basic gage plane
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 64 ? nanya technology corporation nanya reserves the right to change products and specifications without notice. timing diagramspage ac parameters for write timing................................................................................................. .................................41 ac parameters for read timing (3/3/3), bl=4 ............ .............. .............. ........... ........... ........... ........... .......................42 ac parameters for read timing (2/2/2), bl=2 ............ .............. .............. ........... ........... ........... ........... .......................43 ac parameters for read timing (3/2/2), bl=2 ............ .............. .............. ........... ........... ........... ........... .......................44 ac parameters for read timing (3/3/3), bl=2 ............ .............. .............. ........... ........... ........... ........... .......................45 mode register set.............................................................................................................. .........................................46 power on sequence and auto refresh (cbr) ....................................................................................... .....................47 clock suspension / dqm during burst read .............. .............. .............. ........... ........... ........... ........... .......................48 clock suspension / dqm during burst write ................ ..................................................................... .......................49 power down mode and clock suspend ....................... ....................................................................... ........................50 auto refresh (cbr)............................................................................................................. ........................................51 self refresh (entry and exit) .................................................................................................. .....................................52 random row read (interleaving banks) with precharge, bl =8.............. .............. .............. .............. .............. ...........53 random row read (interleaving banks) with auto-precharge, bl=8 ................ .............. .............. ........... .......... .......54 random row write (interleaving banks) with auto-prechar ge, bl=8 ............. .............. .............. ........... ............ ........55 random row write (interleaving banks) with precharge, bl=8... .............. .............. .............. .............. .......... ............56 read/write cycle ........... .............. .............. .............. .............. ............ ........... ........... .......... ................................57 interleaved column read cycle.... .............................................................................................. ................................58 auto precharge after a read burst, bl=4........................................................................................ ...........................59 auto precharge after a write burst, bl=4 ....................................................................................... ............................60 burst read and single write operation .......................................................................................... ............................61 cs function (only cs signal needs to be asserted at minimum rate) ..... ...................................................................62
nt5sv32m8cs nt5sv16m16cs 256mb synchronous dram rev 1.1 consumer oct 2010 65 ? nanya technology corporation cnanya reserves the right to change produ cts and specifications without notice.c please visit our home page for more information: www.nanya.com nanya technology corporation hwa ya technology park 669 fu hsing 3rd rd., kueishan, taoyuan, 333, taiwan, r.o.c. tel: +886-3-328-1688 nanya reserves the right to make changes or deletions without any notice to any of its products. nanya makes no guarantee, warr anty or representation regarding the suitability of its products for any particular purpose. nanya assumes no liability arising out of the application or use of its products. all parameters can and do vary in its application and must be validated for each customer application by the customers te chnician. by purchasing nanya products, nanya d oes not convey any license under its patent rights not the rights of others. na nya products are not designed or intended or authorized for us e in systems intended for the military or surgical implants or any other applications where life is involved or where injury or death may occur or the loss/corruption of data or the loss of system reliability or mission critical applications. should the buyer purchase or use nanya pr oducts in such unintended or unauthorized application, the buyer and user shall indemnify and hold nanya and its officers, employees, subsidiaries, affilia tes and distributors harmless against all claims, costs, damag es, all fees and expenses directly or indirectly arising from any claim of loss, injury or death a ssociated with unintended or unauthorized use even if such claims a lleges nanya was negligent regarding design or manufacture of the part. nanya and the nanya logo are trademarks of the nanya technology corporation. ?2004 nanya technology corporation all rights reserved. printed in taiwan revision log revision date modification 1.0 jun 10, 2010 draft release. 1.1 oct 19, 2010 revised t ck2 parameter.

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